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#ifndef __TWI_SUN20IW3_H__
#define __TWI_SUN20IW3_H__

/** the irq of each TWI **/
#ifdef CONFIG_ARCH_SUN20IW3
#define SUNXI_GIC_START 16
#else
#define SUNXI_GIC_START 0
#endif

/** the base address of TWI*/
#define SUNXI_TWI0_PBASE 0x02502000
#define SUNXI_IRQ_TWI0 (41 - SUNXI_GIC_START)
#define TWI0_SCK GPIOA(16)
#define TWI0_SDA GPIOA(17)
#define TWI0_PIN_MUXSEL 4

#define SUNXI_TWI1_PBASE 0x02502400
#define SUNXI_IRQ_TWI1 (42 - SUNXI_GIC_START)
#define TWI1_SCK GPIOA(14)
#define TWI1_SDA GPIOA(15)
#define TWI1_PIN_MUXSEL 4

#define SUNXI_TWI2_PBASE 0x02502800
#define SUNXI_IRQ_TWI2 (43 - SUNXI_GIC_START)
#define TWI2_SCK GPIOH(5)
#define TWI2_SDA GPIOH(6)
#define TWI2_PIN_MUXSEL 4

#define SUNXI_TWI3_PBASE 0x02502c00
#define SUNXI_IRQ_TWI3 (44 - SUNXI_GIC_START)
#define TWI3_SCK GPIOI(3)
#define TWI3_SDA GPIOI(4)
#define TWI3_PIN_MUXSEL 6

#define SUNXI_TWI4_PBASE 0x02503000
#define SUNXI_IRQ_TWI4 (45 - SUNXI_GIC_START)
#define TWI4_SCK GPIOI(1)
#define TWI4_SDA GPIOI(2)
#define TWI4_PIN_MUXSEL 6

#define TWI_DISABLE_PIN_MUXSEL 15
#define TWI_PULL_STATE 1
#define TWI_DRIVE_STATE 0

#define SUNXI_CLK_TWI(x)	HAL_CLK_PERIPH_TWI##x
#define SUNXI_CLK_RST_TWI(x)	0
/*
#if (defined(CONFIG_ARCH_SUN20IW3) || defined(CONFIG_SOC_SUN20IW1))
#define S_TWI0_SCK GPIOI(0)
#define S_TWI0_SDA GPIOI(1)
#define S_TWI0_PIN_MUXSEL 0
#endif
*/
#endif /*__TWI_SUN20IW3_H__  */

